Full-stack compute at scale, from silicon to power.
Full-stack technology built up over years, co-optimized across engineering disciplines — from the silicon to the power contract — one team accountable for the whole compute solution.
A full-stack fabless that designs the silicon, builds the system and runs the facility.
Walden Block Technology is headquartered in Seoul, with a design engineering branch in Toronto. Our core chip team has worked in blockchain hardware design since 2012, with engineers from wafer foundries, interface IP and chip design companies. Our site operations and power teams bring infrastructure operation and power-contracting experience across several countries. Together, we optimize chip technology, servers, computing centers and power contracts.
Deep silicon understanding.
Design methods native to blockchain silicon raise both performance and yield in HPC and energy-efficient compute chips: more of every wafer ships, and ships at a better point on the energy curve.
- Low-voltage design — logic designed to run well below nominal supply, with per-die voltage tuning: fast and slow dies each settle at their own operating point instead of one fixed-voltage spec, so more of the process distribution meets energy and speed targets and wafer yield rises
- Approximate computing — arithmetic that tolerates rare, bounded errors where the workload allows it, trading exactness for a lower energy per operation
- NoC architecture — a network-on-chip that keeps data movement local and lets each region of the die run at its own voltage and clock, so the chip is not held to the speed of its slowest block
- Yield management — per-die speed and leakage measured through on-die process monitors, with binning and voltage trim set from that data, so the yield gain of low-voltage design is realized in volume
Energy-efficient computing methodology
The methodology takes energy per operation as the design target and applies it at every level of the stack: in the silicon, where low-voltage operation and custom circuits set the energy floor; in the interconnect between die and advanced packaging; and in thermal management, liquid or air, sized to the density the silicon actually runs at. Each level is designed by the same team against the same target.
From silicon to power, one stack, one team.
Walden Stack™ is the full physical layer of compute done in-house: the power contract, the facility, the server and the chip. Each layer is designed against the same target — energy per operation — and each is built to run mining and compute. The two sections below show how it applies to blockchain silicon and to farm-to-AI-ready-IDC upgrades.
Power
Contracted energy, jointly operated with partners, sized for continuous load.
Facility
Mining farms and IDCs on that power — racks, cooling loops, network and control, re-rated to data-center grade.
Server
Liquid- and air-cooled systems assembled to fill the facility, for hashing and for energy-efficient compute.
Silicon
Energy-efficient ASICs, designed to the power, cooling and rack limits of the facility they will run in.
One chain, end to end: design, manufacturing, construction, operation, power contracts.
Upgrading mining farms into AI-ready IDC.
Since ASIC miners first appeared in 2013, blockchain mining has secured a large share of the world’s contracted power — on the order of 140 TWh a year, about 0.5% of global electricity. After the next Bitcoin halving in 2028, proof-of-work demand for that power will fall sharply, and the sites are well suited to become AI-ready computing centers.
The demand is global
Across Sweden, Oman and Malaysia, farm operators hold the two assets that matter most — contracted power and standing facilities — and are looking to convert them into data-center capacity. Walden Block partners with these operators on the upgrade, the equipment and the operation.
Same facility, new workload
The racks, power distribution and airflow that run miners today are what the compute systems are designed into. The facility stays; the machines change.
Our liquid cooling solution
Direct-to-chip two-phase cooling with a phase-change fluid as the heat-transfer medium, designed together with the silicon. Rack density is set by the chip, not limited by the cooling.
- Cold plate — copper microchannel cold plates on the ASICs; the fluid boils inside the plate, so heat leaves as latent heat at a near-constant chip temperature
- Manifold and CDU — server and rack manifolds with quick-disconnect couplings; the coolant distribution unit condenses the vapor back to liquid and hands the heat to the facility water
- Heat rejection — dry coolers or cooling towers, chosen for the site’s climate and water
- Air-cooled option — the same ASICs in an air-cooled chassis for sites that stay on air
Open to co-investment.
Co-investment in facilities
Joint ownership and joint operation of computing sites — power, infrastructure upgrades to AI-ready IDC, and the machines that fill them — with infrastructure operators and investors.
Enquiries
Investor enquiries are handled by the management team in Seoul. Write to [email protected] with the asset or region of interest.
Partners and engineers, write to us directly.
For partnerships, investor relations or engineering roles in Seoul and Toronto, please write to the addresses on the right. Each enquiry is handled by the responsible team.
| Office | City | Role |
|---|---|---|
| HQ | Seoul, Korea | Headquarters · design · operations |
| R&D | Toronto, Canada | Design engineering branch |